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19-4023; Rev 0; 4/06
KIT ATION EVALU E AILABL AV
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
General Description
The MAX1533A/MAX1537A are dual step-down, switchmode power-supply (SMPS) controllers with synchronous rectification, intended for main 5V/3.3V power generation in battery-powered systems. Fixed-frequency operation with optimal interleaving minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Optimal 40/60 interleaving allows the input voltage to go down to 8.3V before duty-cycle overlap occurs, compared to 180 out-of-phase regulators where the duty-cycle overlap occurs when the input drops below 10V. Output current sensing provides accurate current limit using a sense resistor. Alternatively, power dissipation can be reduced using lossless inductor current sensing. Internal 5V and 3.3V linear regulators power the MAX1533A/MAX1537A and their gate drivers, as well as external keep-alive loads, up to a total of 100mA. When the main PWM regulators are in regulation, automatic bootstrap switches bypass the internal linear regulators, providing currents up to 200mA from each linear output. An additional 5V to 23V adjustable internal 150mA linear regulator is typically used with a secondary winding to provide a 12V supply. The MAX1533A/MAX1537A include on-board power-up sequencing, a power-good (PGOOD) output, digital soft-start, and internal soft-shutdown output discharge that prevents negative voltages on shutdown. The MAX1533A is available in a 32-pin 5mm x 5mm thin QFN package, and the MAX1537A is available in a 36pin 6mm x 6mm thin QFN package. The exposed backside pad improves thermal characteristics for demanding linear keep-alive applications. 40/60 Optimal Interleaving Accurate Differential Current-Sense Inputs Internal 5V and 3.3V Linear Regulators with 100mA Load Capability Auxiliary 12V or Adjustable 150mA Linear Regulator (MAX1537A Only) Dual ModeTM Feedback--3.3V/5V Fixed or Adjustable Output (Dual Mode) Voltages 200kHz/300kHz/500kHz Switching Frequency Versatile Power-Up Sequencing Adjustable Overvoltage and Undervoltage Protection 6V to 26V Input Range 2V 0.75% Reference Output Power-Good Output Soft-Shutdown 5A (typ) Shutdown Current
Features
Fixed-Frequency, Current-Mode Control
MAX1533A/MAX1537A
Pin Configurations
SHDN CSH5 CSL5 BST5
SKIP
TOP VIEW
DH5
LX5
32
ON5 ON3 FSEL ILIM3 ILIM5
31
30
29
28
27
IN
26
25 24 23 22 21
FB5 LDO5 DL5 PGND DL3 LDO3 FB3 CSL3
Applications
2 to 4 Li+ Cells Battery-Powered Devices Notebook and Subnotebook Computers PDAs and Mobile Communicators
1 2 3 4 5 6 7 8 9
PGDLY
MAX1533A
20 19 18 17
Ordering Information
PART MAX1533AETJ MAX1533AETJ+ MAX1537AETX TEMP RANGE PIN-PACKAGE -40C to +85C 32 Thin QFN 5mm x 5mm -40C to +85C 32 Thin QFN 5mm x 5mm -40C to +85C 36 Thin QFN 6mm x 6mm
REF GND VCC
10
PGOOD
11
UVP
12
DH3
13
BST3
14
LX3
15
OVP
16
CSH3
MAX1537AETX+ -40C to +85C 36 Thin QFN 6mm x 6mm +Denotes lead-free package.
THIN QFN 5mm x 5mm
Dual Mode is a trademark of Maxim Integrated Products, Inc.
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, INA, LDOA to GND ...............................-0.3V to +30V GND to PGND .......................................................-0.3V to +0.3V LDO5, LDO3, VCC to GND .......................................-0.3V to +6V ILIM3, ILIM5, PGDLY to GND...................................-0.3V to +6V CSL3, CSH3, CSL5, CSH5 to GND ..........................-0.3V to +6V ON3, ON5, FB3, FB5 to GND ..................................-0.3V to +6V SKIP, OVP, UVP to GND...........................................-0.3V to +6V PGOOD, FSEL, ADJA, ONA to GND ........................-0.3V to +6V REF to GND ................................................-0.3V to (VCC + 0.3V) DL3, DL5 to PGND..................................-0.3V to (VLDO5 + 0.3V) BST3, BST5 to PGND .............................................-0.3V to +36V LX3 to BST3..............................................................-6V to +0.3V DH3 to LX3 ..............................................-0.3V to (VBST3 + 0.3V) LX5 to BST5..............................................................-6V to +0.3V DH5 to LX5 ..............................................-0.3V to (VBST5 + 0.3V) LDO3, LDO5 Short Circuit to GND .............................Momentary REF Short Circuit to GND ...........................................Momentary INA Shunt Current.............................................................+15mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 21.3mW/C above +70C) .......1702mW 36-Pin TQFN (derate 26.3mW/C above +70C) .......2105mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES (Note 1) VIN Input Voltage Range VIN Operating Supply Current VIN Standby Supply Current VIN Shutdown Supply Current Quiescent Power Consumption VIN IIN IIN(STBY) IIN(SHDN) PQ LDO5 in regulation IN = LDO5, VOUT5 < 4.43V LDO5 switched over to CSL5 VIN = 6V to 26V, both SMPS off, includes ISHDN VIN = 6V to 26V, SHDN = GND Both SMPS on, FB3 = FB5 = SKIP = GND, VCSL3 = 3.5V, VCSL5 = 5.3V, VINA = 15V, ILDOA = 0, PIN + PCSL3 + PCSL5 + PINA Both SMPS on, FB3 = FB5 = GND, VCSL3 = 3.5V, VCSL5 = 5.3V 6 4.5 15 100 5 3.5 26 5.5 35 170 17 4.5 V A A A mW SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Quiescent Supply Current MAIN SMPS CONTROLLERS 3.3V Output Voltage in Fixed Mode 5V Output Voltage in Fixed Mode Feedback Voltage in Adjustable Mode Output-Voltage Adjust Range FB3, FB5 Dual-Mode Threshold Feedback Input Leakage Current DC Load Regulation
ICC
1.1
2.1
mA
VOUT3 VOUT5 VFB_
VIN = 6V to 26V, SKIP = VCC (Note 2) VIN = 6V to 26V, SKIP = VCC (Note 2) VIN = 6V to 26V, FB3 or FB5, duty factor = 20% to 80% (Note 2) Either SMPS VFB3 = VFB5 = 1.1V Either SMPS, SKIP = VCC, ILOAD = 0 to full load
3.280 4.975 0.990 1.0 0.1 -0.1
3.33 5.05 1.005
3.380 5.125 1.020 5.5 0.2 +0.1
V V V V V A %
-0.1
2
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Line-Regulation Error Operating Frequency (Note 1) fOSC SYMBOL FSEL = GND FSEL = REF FSEL = VCC FSEL = GND Maximum Duty Factor (Note 1) Minimum On-Time SMPS3 to SMPS5 Phase Shift CURRENT LIMIT ILIM_ Adjustment Range Current-Sense Input Range Current-Sense Input Leakage Current Current-Limit Threshold (Fixed) Current-Limit Threshold (Adjustable) Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) Idle-ModeTM Threshold ILIM_ Leakage Current Soft-Start Ramp Time tSS VLIMIT_ VLIMIT_ CSH_, CSL_ CSH_, VCSH_ = 5.5V VCSH_ - VCSL _, ILIM_ = VCC VILIM_ = 2.00V VCSH_ - VCSL_ VILIM_ = 1.00V VILIM_ = 0.50V VNEG VZX VCSH_ - VCSL_, SKIP = VCC, percent of current limit VPGND - VLX_, SKIP = GND, ILIM_ = VCC ILIM_ = VCC VIDLE VCSH_ - VCSL _ With respect to currentlimit threshold (VLIMIT) -0.1 512 / fOSC 10 0.5 0 -1 70 170 91 42 75 200 100 50 -120 3 16 20 +0.1 22 VREF 5.5 +1 80 230 109 58 % mV mV % A s mV V V A mV DMAX tON(MIN) FSEL = REF FSEL = VCC (Note 3) SMPS5 starts after SMPS3 40 144 CONDITIONS Either SMPS, duty cycle = 10% to 90% 170 270 425 91 91 91 MIN TYP 1 200 300 500 93 93 93 200 ns % Deg % 230 330 575 kHz MAX UNITS %
MAX1533A/MAX1537A
ILIM3 = ILIM5 = GND or VCC Measured from the rising edge of ON_ to full scale
INTERNAL FIXED LINEAR REGULATORS LDO5 Output Voltage LDO5 Undervoltage-Lockout Fault Threshold LDO5 Bootstrap Switch Threshold LDO5 Bootstrap Switch Resistance VLDO5 ON3 = ON5 = GND, 6V < VIN < 26V, 0 < ILDO5 < 100mA Rising edge, hysteresis = 1% Rising edge of CSL5, hysteresis = 1% LDO5 to CSL5, VCSL5 = 5V, ILDO5 = 50mA 4.80 3.75 4.41 0.75 4.95 4.0 5.10 4.25 4.75 3 V V V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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3
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER LDO3 Output Voltage LDO3 Bootstrap Switch Threshold LDO3 Bootstrap Switch Resistance Short-Circuit Current Short-Circuit Current (Switched Over to CSL_) LDOA Voltage Range INA Voltage Range LDOA Regulation Threshold, Internal Feedback ADJA Regulation Threshold, External Feedback ADJA Dual-Mode Threshold ADJA Leakage Current LDOA Current Limit Secondary Feedback Regulation Threshold DL Duty Factor INA Quiescent Current INA Shunt Sink Current INA Leakage Current REFERENCE (REF) Reference Voltage Reference Load Regulation REF Lockout Voltage FAULT DETECTION Output Overvoltage Trip Threshold Output Overvoltage FaultPropagation Delay tOVP OVP = GND, with respect to errorcomparator threshold 50mV overdrive 8 11 10 15 % s VREF VCC = 4.5V to 5.5V, IREF = 0 IREF = -10A to +100A VREF(UVLO) Rising edge, hysteresis = 350mV 1.985 1.980 1.95 2.00 2.015 2.020 V V V IINA(SHDN) IINA VADJA = 2.1V VLDOA forced to VINA - 1V, VADJA = 1.9V, VINA > 6V VINA - VLDOA VINA - VLDOA < 0.7V, pulse width with respect to switching period VINA = 24V, ILDOA = no load VINA = 28V VINA = 5V, LDOA disabled 10 30 VADJA VLDOA VINA ADJA = GND, 0 < ILDOA < 120mA, VINA > 13V 0 < ILDOA < 120mA, VLDOA > 5.0V and VINA > VLDOA + 1V SYMBOL VLDO3 CONDITIONS Standby mode, 6V < VIN < 26V, 0 < ILOAD < 100mA Rising edge of CSL3, hysteresis = 1% LDO3 to CSL3, VCSL3 = 3.2V, ILDO3 = 50mA LDO3 = LDO5 = GND, CSL3 = CSL5 = GND LDO3 = LDO5 = GND, VCSL3 > 3.1V, VCSL5 > 4.7V 250 MIN 3.20 2.83 1 150 TYP 3.35 MAX 3.42 3.10 3 220 UNITS V V mA mA
AUXILIARY LINEAR REGULATOR (MAX1537A ONLY) 5 6 11.4 1.94 0.1 -0.1 150 0.65 0.8 33 50 165 0.95 12.0 2.00 0.15 23 24 12.4 2.06 0.2 +0.1 V V V V V A mA V % A mA A
4
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output Undervoltage-Protection Trip Threshold Output Undervoltage FaultPropagation Delay Output Undervoltage-Protection Blanking Time PGOOD Lower Trip Threshold PGOOD Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current PGDLY Pullup Current PGDLY Pulldown Resistance PGDLY Trip Threshold Thermal-Shutdown Threshold GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Dead Time LX_, BST_ Leakage Current INPUTS AND OUTPUTS Logic Input Voltage SKIP, hysteresis = 600mV High Low High Low Logic Input Current SHDN Input Trip Level OVP, UVP, SKIP, ONA Rising trip level Falling trip level Clear fault level/SMPS off level ON_ Input Voltage Delay start level (REF) SMPS on level 1.9 2.4 -1 1.10 0.96 1.6 1 0.7 x VCC 0.4 +1 2.20 1.04 0.8 2.1 V A V 2.4 0.8 V RDH RDL IDH IDL IDL (SINK) tDEAD BST_ - LX_ forced to 5V DL_, high state DL_, low state DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DL_ forced to 2.5V DL_ rising DH_ rising VBST_ = VLX_ = 26V 1.5 1.7 0.6 2 1.7 3.3 35 26 <2 20 5 5 3 A A A ns A TSHDN Hysteresis = 15C REF0.2 IPGOOD_ tPGOOD_ tUVP tBLANK SYMBOL CONDITIONS With respect to error-comparator threshold 50mV overdrive From rising edge of ON_ With respect to error-comparator threshold, hysteresis = 1% Falling edge, 50mV overdrive ISINK = 4mA High state, PGOOD forced to 5.5V PGDLY = GND 4 5 10 REF +160 -14 MIN 65 TYP 70 10 6144 / fOSC -10 10 0.4 1 6 25 REF+ 0.2 -7.5 MAX 75 UNITS % s s % s V A A V C
MAX1533A/MAX1537A
Fault Enable Logic Input Voltage
OVP, UVP, ONA
V
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5
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER FSEL Three-Level Input Logic SYMBOL High REF GND OVP, UVP, SKIP, ONA, ON3, ON5 = GND or VCC SHDN, 0V or 26V FSEL = GND or VCC CSL_ Discharge-Mode On-Resistance CSL_ Synchronous-Rectifier Discharge-Mode Turn-On Level RDISCHARGE 0.2 -1 -1 -3 10 0.3 CONDITIONS MIN VCC - 0.2 1.7 2.3 0.4 +1 +1 +3 25 0.4 V A V TYP MAX UNITS
Input Leakage Current
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER INPUT SUPPLIES (Note 1) VIN Input Voltage Range VIN Operating Supply Current VIN Standby Supply Current VIN Shutdown Supply Current Quiescent Power Consumption VIN IIN IIN(STBY) IIN(SHDN) PQ LDO5 in regulation IN = LDO5, VOUT5 < 4.4V LDO5 switched over to CSL5, either SMPS on VIN = 6V to 26V, both SMPS off, includes ISHDN VIN = 6V to 26V Both SMPS on, FB3 = FB5 = SKIP = GND, VCSL3 = 3.5V, VCSL5 = 5.3V, VINA = 15V, ILDOA = 0, PIN + PCSL3 + PCSL5 + PINA Both SMPS on, FB3 = FB5 = GND, VCSL3 = 3.5V, VCSL5 = 5.3V 6 4.5 26 5.5 35 170 17 4.5 V A A A mW SYMBOL CONDITIONS MIN MAX UNITS
VCC Quiescent Supply Current MAIN SMPS CONTROLLERS 3.3V Output Voltage in Fixed Mode 5V Output Voltage in Fixed Mode Feedback Voltage in Adjustable Mode Output-Voltage Adjust Range FB3, FB5 Adjustable-Mode Threshold Voltage
ICC
2.5
mA
VOUT3 VOUT5 VFB3, VFB5
VIN = 6V to 26V, SKIP = VCC (Note 2) VIN = 6V to 26V, SKIP = VCC (Note 2) VIN = 6V to 26V, FB3 or FB5, duty factor = 20% to 80% (Note 2) Either SMPS Dual-mode comparator
3.28 4.975 0.982 1.0 0.1
3.38 5.125 1.018 5.5 0.2
V V V V V
6
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER Operating Frequency (Note 1) SYMBOL FSEL = GND fOSC FSEL = REF FSEL = VCC FSEL = GND Maximum Duty Factor (Note 1) Minimum On-Time CURRENT LIMIT ILIM_ Adjustment Range Current-Limit Threshold (Fixed) Current-Limit Threshold (Adjustable) VLIMIT_ VLIMIT_ VCSH_ - VCSL _, ILIM_ = VCC VILIM_ = 2.00V VCSH_ - VCSL _ VILIM_ = 1.00V VILIM_ = 0.50V INTERNAL FIXED LINEAR REGULATORS LDO5 Output Voltage LDO5 Undervoltage-Lockout Fault Threshold LDO3 Output Voltage VLDO3 VLDO5 ON3 = ON5 = GND, 6V < VIN < 26V, 0 < ILDO5 < 100mA Rising edge, hysteresis = 1% Standby mode, 6V < VIN < 28V, 0 < ILOAD < 100mA 4.8 3.75 3.20 5.1 4.30 3.43 V V V 0.5 67 170 90 40 VREF 83 230 110 60 mV V mV DMAX tON(MIN) FSEL = REF FSEL = VCC CONDITIONS MIN 170 240 375 91 91 91 250 ns % MAX 230 330 575 kHz UNITS
MAX1533A/MAX1537A
AUXILIARY LINEAR REGULATOR (MAX1537A ONLY) LDOA Voltage Range INA Voltage Range LDOA Regulation Threshold, Internal Feedback ADJA Regulation Threshold, External Feedback ADJA Dual-Mode Threshold Secondary Feedback Regulation Threshold INA Quiescent Current REFERENCE (REF) Reference Voltage VREF VCC = 4.5V to 5.5V, IREF = 0 1.97 2.03 V IINA VADJA VLODA VINA ADJA = GND, 0 < ILDOA < 120mA, VINA > 13V 0 < ILDOA < 120mA, VLDOA > 5.0V and VINA > VLDOA + 1V ADJA VINA - VLDOA VINA = 24V, ILDOA = no load 5 6 11.40 1.94 0.10 0.63 23 24 12.55 2.08 0.25 0.97 165 V V V V V V A
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7
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V, ILDO5 = ILDO3 = ILDOA = no load, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER FAULT DETECTION Output Overvoltage Trip Threshold Output Undervoltage-Protection Trip Threshold PGOOD Lower Trip Threshold PGOOD Output Low Voltage PGDLY Pulldown Resistance PGDLY Trip Threshold GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance INPUTS AND OUTPUTS Logic Input Voltage SKIP, hysteresis = 600mV High Low High Low SHDN Input Trip Level Rising trip level Falling trip level Clear fault level ON_ Input Voltage SMPS off level Delay start level (REF) SMPS on level High FSEL Three-Level Input Logic REF GND 1.9 2.4 VCC - 0.2 1.7 2.3 0.4 V 1.1 0.95 0.7 x VCC 0.4 2.2 1.05 0.8 1.6 2.1 V V 2.4 0.8 V RDH RDL BST_ - LX_ forced to 5V DL_, high state DL_, low state 5 5 3 REF0.2 OVP = GND, with respect to errorcomparator threshold With respect to error-comparator threshold With respect to error-comparator threshold, hysteresis = 1% ISINK = 4mA +8 +65 -14.0 +15 +75 -7.0 0.4 25 REF+ 0.2 % % % V V SYMBOL CONDITIONS MIN MAX UNITS
Fault Enable Logic Input Voltage
OVP, UVP, ONA
V
Note 1: The MAX1533A/MAX1537A cannot operate over all combinations of frequency, input voltage (VIN), and output voltage. For large input-to-output differentials and high-switching frequency settings, the required on-time may be too short to maintain the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1% due to slope compensation. Note 3: Specifications are guaranteed by design, not production tested. Note 4: Specifications to -40C are guaranteed by design, not production tested.
8
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Typical Operating Characteristics
(MAX1537A circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25C, unless otherwise noted.)
MAX1533A/MAX1537A
PWM5 EFFICIENCY vs. LOAD CURRENT (VOUT5 = 5.0V)
MAX1533 toc01
5V OUTPUT VOLTAGE (OUT5) vs. LOAD CURRENT
MAX1533/37 toc02
5V OUTPUT VOLTAGE (OUT5) vs. INPUT VOLTAGE
NO LOAD
MAX1533/37 toc03
100
5.12 5.08 OUTPUT VOLTAGE (V) 5.04 5.00 4.96 4.92 4.88 SKIP = GND SKIP = VCC
5.12 5.08 OUTPUT VOLTAGE (V) 5.04 5.00 4.96 4.92 4.88
90 EFFICIENCY (%)
80
VIN = 7V VIN = 12V VIN = 20V
70
60 SKIP = GND SKIP = VCC 0.01 0.1 1 10
50
SKIP = GND SKIP = VCC 5 10 15 20 25 30
0
1
2
3
4
5
6
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
PWM3 EFFICIENCY vs. LOAD CURRENT (VOUT3 = 3.3V)
MAX1533/37 toc04
3.3V OUTPUT VOLTAGE (OUT3) vs. LOAD CURRENT
MAX1533/37 toc05
3.3V OUTPUT VOLTAGE (OUT3) vs. INPUT VOLTAGE
NO LOAD
MAX1533/37 toc06
100
3.39 3.36 OUTPUT VOLTAGE (V) 3.33 3.30 3.27 3.24 3.21 SKIP = GND SKIP = VCC
3.39 3.36 OUTPUT VOLTAGE (V) 3.33 3.30 3.27 3.24 3.21
90 EFFICIENCY (%) VIN = 5V
80
70
VIN = 12V VIN = 20V SKIP = GND SKIP = VCC
60
SKIP = GND SKIP = VCC 5 10 15 20 25 30
50 0.01 0.1 1 10 LOAD CURRENT (A)
0
1
2
3
4
5
6
LOAD CURRENT (A)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FULLY ENABLED)
MAX1533/37 toc07
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (STANDBY MODE)
MAX1533/37 toc08
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE
SHDN = GND SHUTDOWN SUPPLY CURRENT (A) 8
MAX1533/37 toc09
32 ON3 = ON5 = VCC 28 SUPPLY CURRENT (mA) 24 20 16 12 8 4 0 0 5 10 15 20 25 0.22mA (VIN = 12V) SKIP = GND SKIP = VCC
1.0 0.9 STANDBY SUPPLY CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ON3 = ON5 = GND
10
6
4
2
0 0 5 10 15 20 25 30 0 5 10 15 20 25 30 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
30
INPUT VOLTAGE (V)
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25C, unless otherwise noted.)
IDLE-MODE CURRENT vs. INPUT VOLTAGE
MAX1533/37 toc10
2.0V REFERENCE LOAD REGULATION
MAX1533 toc11
LINEAR-REGULATOR LOAD REGULATION
MAX1533/37 toc12
3.5 3.0 PEAK CURRENT (A) 2.5 2.0 1.5 1.0 0.5 5V OUTPUT 0 0 5 10 15 20 25 DUTY CYCLE LIMITED
2.02
50 LDO DEVIATION VOLTAGE (mV)
2.01 REF VOLTAGE (V)
0
LDO3 LDO5
-50
2.00
-100
1.99
-150 VIN = 6V ON3 = ON5 = GND -200
1.98 30 -20 0 20 40 60 80 100 INPUT VOLTAGE (V) REF LOAD CURRENT (A)
0
20
40
60
80
100
120
140
LDO LOAD CURRENT (mA)
AUXILIARY LINEAR-REGULATOR LOAD REGULATION
MAX1533/37 toc13
INTERLEAVED OPERATION
MAX1533/37 toc14
LINEAR-REGULATOR STARTUP WAVEFORMS
MAX1533/37 toc15
12.1
12V A 0 5V 0 B
5V A 0 4V B 2V C D 0 2V 0 2V E F 2.0s/div A. LX5, 10V/div B. 5V OUTPUT, 100mV/div C. PWM5 INDUCTOR CURRENT, 5A/div D. LX3, 10V/div E. 3.3V OUTPUT, 100mV/div F. PWM3 INDUCTOR CURRENT, 5A/div 0 400s/div A. SHDN, 5V/div B. LDO5, 2V/div C. LDO3, 2V/div D. REF, 2V/div 100 LOAD ON LDO5 AND LDO3 D C
AUX LDO VOLTAGE (V)
12.0
11.9
12V 0
11.8
3.3V 0
11.7 0 40 80 120 160 200 LDOA LOAD CURRENT (mA)
10
______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25C, unless otherwise noted.)
MAX1533A/MAX1537A
DELAYED STARTUP WAVEFORM (LIGHT LOAD)
MAX1533/37 toc16
STARTUP WAVEFORM (HEAVY LOAD)
MAX1533/37 toc17
SHUTDOWN WAVEFORM (NO LOAD)
MAX1533/37 toc18
3.3V 0 5V A
3.3V 0 4V
A
2V 0 5V 0 5V
A B
B 2V 0 3.3V 0 2.5A 0 5V D 0 2ms/div A. ON5, 5V/div B. 5V OUTPUT, 2V/div C. 3.3V OUPUT, 2V/div D. PGOOD, 2V/div 100 LOAD ON OUT5 AND OUT3, ON3 = REF 0 400s/div A. ON5, 5V/div B. 5V OUTPUT, 2V/div C. INDUCTOR CURRENT, 5A/div D. LDO5, 1V/div E. DL5, 5V/div 1.0 LOAD
B
C C D E 0 3.3V 0 5V E 0 0 2ms/div A. SHDN, 5V/div D. 3.3V OUTPUT, 5V/div B. 5V OUTPUT, 5V/div E. DL3, 5V/div C. DL5, 5V/div F. PGOOD, 5V/div ON3 = ON5 = VCC, OVP = GND F D
C
0
SHUTDOWN WAVEFORM (1 LOAD)
MAX1533/37 toc19
5V OUTPUT LOAD TRANSIENT (FORCED-PWM)
MAX1533/37 toc20
3.3V OUTPUT LOAD TRANSIENT (FORCED-PWM)
MAX1533/37 toc21
2V 0 5V 5V
A B
4A 0
A
4A 0
A
5V C 5A 0 5V E 0 100s/div A. SHDN, 5V/div B. LDO5, 2V/div C. 5V OUTPUT, 2V/div D. INDUCTOR CURRENT, 5A/div E. DL5, 5V/div ON3 = ON5 = VCC, OVP = GND 0 40s/div A. IOUT5 = 0.2A TO 4A, 5A/div B. VOUT5 = 5.0V, 100mV/div C. INDUCTOR CURRENT, 5A/div D. LX5, 10V/div SKIP = VCC D 4A
B
3.3V 4A
B
C 0 12V D
0 12V
C
D 0 40s/div A. IOUT3 = 0.2A TO 4A, 5A/div B. VOUT3 = 3.3V, 100mV/div C. INDUCTOR CURRENT, 5A/div D. LX3, 10V/div SKIP = VCC
______________________________________________________________________________________
11
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25C, unless otherwise noted.)
3.3V OUTPUT LOAD TRANSIENT (PULSE SKIPPING)
MAX1533/37 toc22
OUTPUT OVERLOAD (UVP ENABLED)
MAX1533/37 toc23
LDO5 LOAD TRANSIENT
MAX1533/37 toc24
4A 0 3.3V
A
5V 0 3.3V
A B
5V 0 100mA
A
B 0 30A
B C 0
4A 0 12V D 0 40s/div A. IOUT3 = 0.2A TO 4A, 5A/div B. VOUT3 = 3.3V, 100mV/div C. INDUCTOR CURRENT, 5A/div D. LX3, 10V/div SKIP = GND C 0 7A 0 12V 0 4s/div A. PGOOD2, 5V/div B. 3.3V OUTPUT, 3.3V/div C. LOAD (0 TO 30A), 20A/div
D E
5.0V 4.95V 20s/div A. CONTROL SIGNAL, 5V/div B. ILDO5 = 1mA TO 100mA, 100mA/div C. LDO5, 50m/div ON3 = ON5 = GND
C
D. INDUCTOR CURRENT, 10A/div E. LX3, 20V/div
LDO5 LINE TRANSIENT
MAX1533/37 toc25
AUXILIARY LINEAR-REGULATOR LOAD TRANSIENT
MAX1533/37 toc26
20V 15V 10V 5V 5.05V 5.00V 4.95V B A
120mA 10mA
A
14V 13V 11.96V 11.90V C B
20s/div A. INPUT VOLTAGE (VIN = 7V TO 20V), 5V/div B. LDO5 OUTPUT VOLTAGE, 50mV/div ON3 = ON5 = GND, ILDO5 = 20mA
100s/div A. ILDOA = 10mA TO 100mA, 100mA/div B. INA, 1V/div C. LDOA, 50mV/div INA = VOLTAGE GENERATED BY SECONDARY TRANSFORMER WINDING
12
______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Pin Description
PIN MAX1533A MAX1537A NAME FUNCTION Auxiliary Feedback Input. Connect a resistive voltage-divider from LDOA to analog ground to adjust the auxiliary linear-regulator output voltage. ADJA regulates at 2V. Connect ADJA to GND for nominal 12V output using internal feedback. 5V SMPS Enable Input. The 5V SMPS is enabled if ON5 is greater than the SMPS on level and disabled if ON5 is less than the SMPS off level. If ON5 is connected to REF, the 5V SMPS starts after the 3.3V SMPS reaches regulation (delay start). Drive ON5 below the clear fault level to reset the fault latches. 3.3V SMPS Enable Input. The 3.3V SMPS is enabled if ON3 is greater than the SMPS on level and disabled if ON3 is less than the SMPS off level. If ON3 is connected to REF, the 3.3V SMPS starts after the 5V SMPS reaches regulation (delay start). Drive ON3 below the clear fault level to reset the fault latches. LDOA Enable Input. When ONA is low, LDOA is high impedance and the secondary winding control is off. When ONA is high, LDOA is on. Connect to LDO3, LDO5, CSL3, CSL5, or other output for desired automatic startup sequencing. Frequency-Select Input. This three-level logic input sets the controller's switching frequency. Connect to GND, REF, or VCC to select the following typical switching frequencies: VCC = 500kHz, REF = 300kHz, GND = 200kHz 3.3V SMPS Peak Current-Limit Threshold Adjustment. The current-limit threshold defaults to 75mV if ILIM3 is connected to VCC. In adjustable mode, the current-limit threshold across CSH3 and CSL3 is precisely 1/10 the voltage seen at ILIM3 over a 500mV to 2.0V range. The logic threshold for switchover to the 75mV default value is approximately VCC - 1V. 5V SMPS Peak Current-Limit Threshold. The current-limit threshold defaults to 75mV if ILIM5 is connected to VCC. In adjustable mode, the current-limit threshold across CSH5 and CSL5 is precisely 1/10th the voltage seen at ILIM5 over a 500mV to 2.0V range. The logic threshold for switchover to the 75mV default value is approximately VCC - 1V. 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1F or greater ceramic capacitor. The reference can source up to 100A for external loads. Loading REF degrades output-voltage accuracy according to the REF load-regulation error. The reference shuts down when SHDN is low. Analog Ground. Connect the backside pad to GND. Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20 resistor. Bypass VCC to analog ground with a 1F or greater ceramic capacitor. Power-Good One-Shot Delay. Place a timing capacitor on PGDLY to delay PGOOD going high. PGDLY has a 5A pullup current and a 10 pulldown. The pulldown is activated when power is not good. When power is good, the pulldown is shut off and the 5A pullup is activated. When PGDLY crosses REF, PGOOD is enabled.
MAX1533A/MAX1537A
--
1
ADJA
1
2
ON5
2
3
ON3
--
4
ONA
3
5
FSEL
4
6
ILIM3
5
7
ILIM5
6
8
REF
7 8
9 10
GND VCC
9
11
PGDLY
______________________________________________________________________________________
13
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Pin Description (continued)
PIN MAX1533A MAX1537A NAME FUNCTION Open-Drain Power-Good Output. PGOOD is low if either output is more than 10% (typ) below the normal regulation point, during soft-start, and in shutdown. PGOOD is delayed on the rising edge by the PGDLY one-shot timer. PGOOD becomes high impedance when both SMPS outputs are in regulation. Undervoltage Fault-Protection Control. Connect UVP to GND to select the default overvoltage threshold of 70% of nominal. Connect to VCC to disable undervoltage protection and clear the undervoltage fault latch. High-Side Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to BST3. Boost Flying-Capacitor Connection for 3.3V SMPS. Connect to an external capacitor and diode as shown in Figure 6. An optional resistor in series with BST3 allows the DH3 pullup current to be adjusted. Inductor Connection for 3.3V SMPS. Connect LX3 to the switched side of the inductor. LX3 serves as the lower supply rail for the DH3 high-side gate driver. Overvoltage Fault-Protection Control. Connect OVP to GND to select the default overvoltage threshold of +11% above nominal. Connect to VCC to disable overvoltage protection and clear the overvoltage fault latch. Positive Current-Sense Input for 3.3V SMPS. Connect to the positive terminal of the current-sense element. Figure 9 describes two different current-sensing options. Negative Current-Sense Input for 3.3V SMPS. Connect to the negative terminal of the current-sense element. Figure 9 describes two different current-sensing options. CSL3 also serves as the bootstrap input for LDO3. Feedback Input for 3.3V SMPS. Connect to GND for fixed 3.3V output. In adjustable mode, FB3 regulates to 1V. 3.3V Internal Linear-Regulator Output. Bypass with 2.2F (min) (1F/20mA). Provides 100mA (min). Power is taken from LDO5. If CSL3 is greater than 3V, the linear regulator shuts down and LDO3 connects to CSL3 through a 1 switch rated for loads up to 200mA. Low-Side Gate-Driver Output for 3.3V SMPS. DL3 swings from PGND to LDO5. Power Ground Low-Side Gate-Driver Output for 5V SMPS. DL5 swings from PGND to LDO5. 5V Internal Linear-Regulator Output. Bypass with 2.2F (min) (1F/20mA). Provides power for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST diodes, the PWM controller, logic, and reference through the VCC pin, as well as the LDO3 internal 3.3V linear regulator. Provides 100mA (min) for external loads (+25mA for gate drivers). If CSL5 is greater than 4.5V, the linear regulator shuts down and LDO5 connects to CSL5 through a 0.75 switch rated for loads up to 200mA. Feedback Input for 5V SMPS. Connect to GND for fixed 5V output. In adjustable mode, FB5 regulates to 1V.
10
12
PGOOD
11 12 13
13 14 15
UVP DH3 BST3
14
16
LX3
15
17
OVP
16
18
CSH3
17
19
CSL3
18
20
FB3
19
21
LDO3
20 21 22
22 23 24
DL3 PGND DL5
23
25
LDO5
24
26
FB5
14
______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Pin Description (continued)
PIN MAX1533A MAX1537A NAME FUNCTION Negative Current-Sense Input for 5V SMPS. Connect to the negative terminal of the current-sense element. Figure 9 describes two different current-sensing options. CSL5 also serves as the bootstrap input for LDO5. Positive Current-Sense Input for 5V SMPS. Connect to the positive terminal of the current-sense element. Figure 9 describes two different current-sensing options. Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to PGND with 0.22F close to the IC. Inductor Connection for 5V SMPS. Connect LX5 to the switched side of the inductor. LX5 serves as the lower supply rail for the DH5 high-side gate driver. Boost Flying-Capacitor Connection for 5V SMPS. Connect to an external capacitor and diode as shown in Figure 6. An optional resistor in series with BST5 allows the DH5 pullup current to be adjusted. High-Side Gate-Driver Output for 5V SMPS. DH5 swings from LX5 to BST5. Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connect to GND for high-efficiency pulse-skipping mode at light loads. Shutdown Control Input. The device enters its 5A supply-current shutdown mode if VSHDN is less than the SHDN input falling-edge trip level and does not restart until VSHDN is greater than the SHDN input rising-edge trip level. Connect SHDN to VIN for automatic startup. SHDN can be connected to VIN through a resistive voltage-divider to implement a programmable undervoltage lockout. Supply Voltage Input for the Auxiliary LDOA Linear Regulator. INA is clamped with an internal shunt to 26V. Adjustable (12V Nominal) 150mA Auxiliary Linear-Regulator Output. Input supply comes from INA. Bypass LDOA to GND with 2.2F (min) (1F/20mA). Secondary feedback threshold is set at INA - LDOA = 0.8V, and triggers the DL5 on the 5V SMPS only. ONA high enables regulator output and secondary regulation. PGOOD is not affected by the state of LDOA.
MAX1533A/MAX1537A
25
27
CSL5
26 27 28
28 29 30
CSH5 IN LX5
29 30 31
31 32 33
BST5 DH5 SKIP
32
34
SHDN
--
35
INA
--
36
LDOA
______________________________________________________________________________________
15
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Table 1. Component Selection for Standard Applications
COMPONENT Input Voltage CIN_, Input Capacitor COUT5, Output Capacitor COUT3, Output Capacitor NH_ High-Side MOSFET NL_ Low-Side MOSFET DL_ Schottky Rectifier (if needed) Inductor/Transformer 5A/300kHz VIN = 7V to 24V (2) 10F, 25V Taiyo Yuden TMK432BJ106KM 150F, 6.3V, 40m, low-ESR capacitor Sanyo 6TPB150ML 220F, 4V, 40m, low-ESR capacitor Sanyo 4TPB220ML Fairchild Semiconductor FDS6612A International Rectifier IRF7807V Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 2A, 30V, 0.45Vf Nihon EC21QS03L T1 = 6.8H, 1:2 turns Sumida 4749-T132 L1 = 5.8H, 8.6A Sumida CDRH127-5R8NC 10m 1%, 0.5W resistor IRC LR2010-01-R010F or Dale WSL-2010-R010F 5A/500kHz VIN = 7V to 24V (2) 10F, 25V Taiyo Yuden TMK432BJ106KM 150F, 6.3V, 40m, low-ESR capacitor Sanyo 6TPB150ML 220F, 4V, 40m, low-ESR capacitor Sanyo 4TPB220ML Fairchild Semiconductor FDS6612A International Rectifier IRF7807V Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 2A, 30V, 0.45Vf Nihon EC21QS03L 3.9H Sumida CDRH124-3R9NC 10m 1%, 0.5W resistor IRC LR2010-01-R010F or Dale WSL-2010-R010F
RCS
Table 2. Component Suppliers
SUPPLIER AVX Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet WEBSITE www.avx.com www.centralsemi.com www.coilcraft.com www.coiltronics.com www.fairchildsemi.com www.irf.com www.kemet.com Sanyo Sumida Taiyo Yuden TDK TOKO Vishay (Dale, Siliconix) SUPPLIER Panasonic WEBSITE www.panasonic.com/industrial www.secc.co.jp www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.vishay.com
Detailed Description
The MAX1533A/MAX1537A standard application circuit (Figure 1) generates the 5V/5A and 3.3V/5A typical of the main supplies in a notebook computer. The input supply range is 7V to 24V. See Table 1 for component selections and Table 2 for component manufacturers. The MAX1533A/MAX1537A contain two interleaved fixed-frequency step-down controllers designed for lowvoltage power supplies. The optimal interleaved architecture guarantees out-of-phase operation, reducing the input capacitor ripple. Two internal LDOs generate the keep-alive 5V and 3.3V power. The MAX1537A has an auxiliary LDO that can be configured to the preset 12V output or an adjustable output.
16
Fixed Linear Regulators (LDO5 and LDO3)
Two internal linear regulators produce preset 5V (LDO5) and 3.3V (LDO3) low-power outputs. LDO5 powers LDO3, the gate drivers for the external MOSFETs, and provides the bias supply (VCC) required for the SMPS analog control, reference, and logic blocks. LDO5 supplies at least 100mA for external and internal loads, including the MOSFET gate drive, which typically varies from 5mA to 50mA, depending on the switching frequency and external MOSFETs selected. LDO3 also supplies at least 100mA for external loads. Bypass LDO5 and LDO3 with a 2.2F or greater output capacitor, using an additional 1.0F per 20mA of internal and external load.
______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
5V LDO OUTPUT INPUT (VIN) C1 10F DBST NH1 CBST 0.1F DH3 BST3 LX3 L1 5.8H DL1 NL1 PGND GND RCS1 10m CSH3 3.3V PWM OUTPUT CSL3 COUT1 220F 40m CREF 0.22F R2 100k ILIM3 R5 60.4k ON OFF ON OFF ON5 R4 100k ILIM5 SHDN ON3 PGOOD PGDLY LDO3 C3 10F 3.3V LDO OUTPUT FB3 OVP REF CSH5 CSL5 FB5 UVP SKIP FSEL VCC R1 C2 1F 20 R8 100k POWER-GOOD REF (300kHz) CONNECT TO LDO5 COUT2 150F 40m RCS2 10m 5V PWM OUTPUT DL3 MAX1533A MAX1537A DH5 BST5 CBST 0.1F LX5 DL5 DL2 NL2 CIN (2) 10F
LDO5
IN DBST NH2
C5 22F SECONDARY OUTPUT D1
T1 1:2 TURNS LP = 6.8H
R3 60.4k
MAX1537A ONLY SECONDARY OUTPUT ON OFF INA ONA ADJA R7 0 POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS ANALOG GROUND LDOA R6 OPEN C4 10F 12V LDO OUTPUT
Figure 1. MAX1533A/MAX1537A Standard Application Circuit ______________________________________________________________________________________ 17
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
SMPS to LDO Bootstrap Switchover When the 5V main output voltage is above the LDO5 bootstrap-switchover threshold, an internal 0.75 (typ) p-channel MOSFET shorts CSL5 to LDO5 while simultaneously shutting down the LDO5 linear regulator. Similarly, when the 3.3V main output voltage is above the LDO3 bootstrap-switchover threshold, an internal 1 (typ) p-channel MOSFET shorts CSL3 to LDO3 while simultaneously shutting down the LDO3 linear regulator. These actions bootstrap the device, powering the internal circuitry and external loads from the output SMPS voltages, rather than through linear regulators from the battery. Bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing power from a 90%-efficient switch-mode source, rather than from a much-less-efficient linear regulator. The output current limit increases to 200mA when the LDO_ outputs are switched over. SMPS 5V Bias Supply (LDO5 and VCC) The A switch-mode power supplies (SMPS) require a 5V bias supply in addition to the high-power input supply (battery or AC adapter). This 5V bias supply is generated by the MAX1533A/MAX1537As' internal 5V linear regulator (LDO5). This bootstrapped LDO allows the MAX1533A/MAX1537A to power-up independently. The gate-driver input supply is connected to the fixed 5V linear-regulator output (LDO5). Therefore, the 5V LDO supply must provide V CC (PWM controller) and the gate-drive power, so the maximum supply current required is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 5mA to 50mA (typ) where ICC is 1mA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet's total gate-charge specification limits at VGS = 5V.
System Enable/Shutdown (SHDN)
Drive SHDN below the precise SHDN input falling-edge trip level to place the MAX1533A/MAX1537A in their low-power shutdown state. The MAX1533A/MAX1537A consume only 5A of quiescent current while in shutdown mode. When shutdown mode activates, the reference turns off, making the threshold to exit shutdown less accurate. To guarantee startup, drive SHDN above 2.2V (SHDN input rising-edge trip level). For automatic shutdown and startup, connect SHDN to VIN. The accurate 1V falling-edge threshold on SHDN can be used to detect a specific input-voltage level and shut the device down. Once in shutdown, the 1.6V rising-edge threshold activates, providing sufficient hysteresis for most applications.
SMPS Detailed Description
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above approximately 1V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are pulled low if OVP is disabled (OVP = VCC), or driven high if OVP is enabled (OVP = GND) until the SMPS controllers are activated. The VCC input undervoltage-lockout (UVLO) circuitry inhibits switching if the 5V bias supply (LDO5) is below the 4V input UVLO threshold. Once the 5V bias supply (LDO5) rises above this input UVLO threshold and the controllers are enabled, the SMPS controllers start switching and the output voltages begin to ramp up using soft-start. The internal digital soft-start gradually increases the internal current-limit level during startup to reduce the input surge currents. The MAX1533A/MAX1537A divide the soft-start period into five phases. During the first phase, each controller limits its current limit to only 20% of its full current limit. If the output does not reach regulation within 128 clock cycles (1 / fOSC), soft-start enters the second phase and the current limit is increased by another 20%. This process repeats until the maximum current limit is reached after 512 clock cycles (1 / fOSC) or when the output reaches the nominal regulation voltage, whichever occurs first (see the startup waveforms in the Typical Operating Characteristics).
Reference (REF)
The 2V reference is accurate to 1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.22F or greater ceramic capacitor. The reference sources up to 100A and sinks 10A to support external loads. If highly accurate specifications (0.5%) are required for the main SMPS output voltages, the reference should not be loaded. Loading the reference reduces the LDO5, LDO3, OUT5, and OUT3 output voltages slightly because of the reference load-regulation error.
18
______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
LDO3 3.3V LINEAR REGULATOR SHDN 5V LINEAR REGULATOR IN LDO5
FSEL
OSC
LDO BYPASS CIRCUITRY
LDO BYPASS CIRCUITRY
SKIP ILIM5 ILIM3 CSH3 CSL3 BST3 DH3 LX3 LDO5 DL3 PGND FB DECODE (FIGURE 5) INTERNAL FB PWM3 CONTROLLER (FIGURE 3) PWM5 CONTROLLER (FIGURE 3) LDO5 DL5 CSH5 CSL5 BST5 DH5 LX5
FB3
FB DECODE (FIGURE 5)
FB5
ON5
ON3
REF R 2.0V REF R VCC GND
OVP UVP PGDLY PGOOD POWER-GOOD AND FAULT PROTECTION (FIGURE 7)
SECONDARY FEEDBACK
MAX1537A AUXILIARY LINEAR REGULATOR (FIGURE 8)
FAULT
INA LDOA ADJA ONA
MAX1533A/MAX1537A
Figure 2. MAX1533A/MAX1537A Functional Diagram ______________________________________________________________________________________ 19
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Table 3. Operating Modes
MODE Shutdown Mode Standby Mode Normal Operation 3.3V SMPS Active 5V SMPS Active Normal Operation (Delayed 5V SMPS Startup) INPUTS* SHDN LOW HIGH HIGH HIGH HIGH ON5 X LOW HIGH LOW HIGH ON3 X LOW HIGH HIGH LOW LDO5 OFF ON ON ON ON LDO3 OFF ON ON ON ON OUTPUTS 5V SMPS OFF OFF ON OFF ON ON Power-up after 3.3V SMPS is in regulation 3V SMPS OFF OFF ON ON OFF
HIGH
REF
HIGH
ON
ON
ON
Normal Operation (Delayed 3.3V SMPS Startup)
HIGH
HIGH
REF
ON
ON
ON
ON Power-up after 5V SMPS is in regulation
*SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3 and ON5 are 3-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the middle logic level is between 1.9V and 2.1V (see the Electrical Characteristics table).
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing. ON3 or ON5 rising above 2.4V enables the respective outputs. ON3 or ON5 falling below 1.6V disables the respective outputs. Driving ON_ below 0.8V clears the overvoltage, undervoltage, and thermal fault latches. SMPS Power-Up Sequencing Connecting ON3 or ON5 to REF forces the respective outputs off while the other output is below regulation and starts after that output regulates. The second SMPS remains on until the first SMPS turns off, the device shuts down, a fault occurs, or LDO5 goes into undervoltage lockout. Both supplies begin their power-down sequence immediately when the first supply turns off. Output Discharge (Soft-Shutdown) When output discharge is enabled (OVP pulled low) and the switching regulators are disabled--by transitions into standby or shutdown mode, or when an output undervoltage fault occurs--the controller discharges both outputs through internal 12 switches, until the output voltages decrease to 0.3V. This slowly discharges the output capacitance, providing a softdamped shutdown response. This eliminates the slightly negative output voltages caused by quickly discharging the output through the inductor and lowside MOSFET. When an SMPS output discharges to
0.3V, its low-side driver (DL_) is forced high, clamping the respective SMPS output to GND. The reference remains active to provide an accurate threshold and to provide overvoltage protection. Both SMPS controllers contain separate soft-shutdown circuits. When output discharge is disabled (OVP = VCC), the lowside drivers (DL_) and high-side drivers (DH_) are both pulled low, forcing LX into a high-impedance state. Since the outputs are not actively discharged by the SMPS controllers, the output-voltage discharge rate is determined only by the output capacitance and load current.
Fixed-Frequency, Current-Mode PWM Controller
The heart of each current-mode PWM controller is a multiinput, open-loop comparator that sums two signals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (Figure 3). The MAX1533A/MAX1537A use a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. The MAX1533A/ MAX1537A use a relatively low loop gain, allowing the use of low-cost output capacitors. The low loop gain results in the -0.1% typical load-regulation error and helps reduce the output capacitor size and cost by shifting the unity-gain crossover frequency to a lower level.
20
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
CSH CSL REF / 2 SLOPE COMP FROM FB (SEE FIGURE 5)
0.2 x VLIMIT
AGND
R
IDLEMODE CURRENT
Q S
DH DRIVER
SKIP
SOFT-START ON COUNTER DAC CURRENT LIMIT
OSC
-1.2 x VLIMIT
S R
Q DL DRIVER
LX
PGND
MAX1537A ONLY
0.8V ONE-SHOT SECONDARY FEEDBACK
Figure 3: PWM-Controller Functional Diagram
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Frequency Selection (FSEL)
The FSEL input selects the PWM-mode switching frequency. Table 4 shows the switching frequency based on FSEL connection. High-frequency (500kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. Idle-Mode Current-Sense Threshold The on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current-sense threshold. Under light-load conditions, the on-time duration depends solely on the idle-mode current-sense threshold, which is approximately 20% of the full-load current-limit threshold set by ILIM_. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 4). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFET (PGND to LX_). Once VPGND - VLX_ drops below the 3mV zero-crossing current-sense threshold, the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the "critical conduction" point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is given by: ILOAD(SKIP) = VOUT (VIN - VOUT ) 2 x VIN x fSW x L
Forced-PWM Mode
The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side switch on-time. This forces the low-side gate-drive waveform to constantly be the complement of the high-side gatedrive waveform, so the inductor current reverses at light loads while DH_ maintains a duty factor of VOUT / VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V supply current remains between 15mA and 50mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is most useful for avoiding audiofrequency noise and improving load-transient response. Since forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads.
Light-Load Operation Control (SKIP)
The MAX1533A/MAX1537A include a light-load operating-mode control input (SKIP) used to independently enable or disable the zero-crossing comparator for both controllers. When the zero-crossing comparator is enabled, the controller forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under lightload conditions to avoid overcharging the output. When the zero-crossing comparator is disabled, the controller is forced to maintain PWM operation under light-load conditions (forced-PWM).
Table 4. FSEL Configuration Table
FSEL VCC REF GND SWITCHING FREQUENCY 500kHz 300kHz 200kHz
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).
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TO ERROR AMPLIFIER ADJUSTABLE OUTPUT
FB
INDUCTOR CURRENT
IL tON(SKIP) IDLE VIN - VOUT
REF (2.0V) 12R
R ILOAD(SKIP) CSL 0 ON-TIME TIME
FIXED OUTPUT FB = GND
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Figure 5. Dual-Mode Feedback Decoder
Output Voltage
DC output accuracy specifications in the Electrical Characteristics table refer to the error-comparator's threshold. When the inductor continuously conducts, the MAX1533A/MAX1537A regulate the peak of the output ripple, so the actual DC output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. For PWM operation (continuous conduction), the output voltage is accurately defined by the following equation: ASLOPE VNOM VRIPPLE VOUT(PWM ) = VNOM 1 - VIN 2 where V NOM is the nominal output voltage, A SLOPE equals 1%, and VRIPPLE is the output ripple voltage (V RIPPLE = ESR x I INDUCTOR as described in the Output Capacitor Selection section). In discontinuous conduction (IOUT < ILOAD(SKIP)), the MAX1533A/MAX1537A regulate the valley of the output ripple, so the output voltage has a DC regulation level higher than the error-comparator threshold. For PFM operation (discontinuous conduction), the output voltage is approximately defined by the following equation: VOUT(PFM ) = VNOM +
1 fSW IIDLE x ESR 2 fOSC
where VNOM is the nominal output voltage, fOSC is the maximum switching frequency set by the internal oscillator, fSW is the actual switching frequency, and IIDLE is the idle-mode inductor current when pulse skipping. Adjustable/Fixed Output Voltages (Dual-Mode Feedback) Connect FB3 and FB5 to GND to enable the fixed SMPS output voltages (3.3V and 5V, respectively), set by a preset, internal resistive voltage-divider connected between CSL_ and analog ground. Connect a resistive voltage-divider at FB_ between CSL_ and GND to adjust the respective output voltage between 1V and 5.5V (Figure 5). Choose R2 (resistance from FB to GND) to be about 10k and solve for R1 (resistance from OUT to FB) using the equation: VOUT _ R1 = R2 - 1 VFB _ where VFB_ = 1V nominal.
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
When adjusting both output voltages, set the 3.3V SMPS lower than the 5V SMPS. LDO5 connects to the 5V output (CSL5) through an internal switch only when CSL5 is above the LDO5 bootstrap threshold (4.56V). Similarly, LDO3 connects to the 3.3V output (CSL3) through an internal switch only when CSL3 is above the LDO3 bootstrap threshold (2.91V). Bootstrapping works most effectively when the fixed output voltages are used. Once LDO_ is bootstrapped from CSL_, the internal linear regulator turns off. This reduces internal power dissipation and improves efficiency at higher input voltage.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN V OUT differential exists. The high-side gate drivers (DH_) source and sink 2A, and the low-side gate drivers (DL_) source 1.7A and sink 3.3A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by diode-capacitor charge pumps at BST_ (Figure 6) while the DL_ synchronous-rectifier drivers are powered directly by the fixed 5V linear regulator (LDO5). Adaptive dead-time circuits monitor the DL_ and DH_ drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX1533A/ MAX1537A interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 to 100 mils wide if the MOSFET is 1 inch from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.6 (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gate-to-source capacitance to ensure fastrising LX_ edges do not pull up the low-side MOSFETs' gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFET's gate-to-drain capacitance (CRSS), gate-tosource capacitance (C ISS - C RSS ), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS CISS Lot-to-lot variation of the threshold voltage may cause problems in marginal designs. Alternatively, adding a resistor less than 10 in series with BST_ may remedy the problem by increasing the turn-on time of the highside MOSFET without degrading the turn-off time (Figure 6).
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense inputs (CSH_ and CSL_) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold, the PWM controller turns off the high-side MOSFET (Figure 3). At the next rising edge of the internal oscillator, the PWM controller does not initiate a new cycle unless the current-sense signal drops below the current-limit threshold. The actual maximum load current is less than the peak current-limit threshold by an amount equal to half of the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (VOUT / VIN). In forced-PWM mode, the MAX1533A/MAX1537A also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM_ is adjusted. Connect ILIM_ to VCC for the 75mV default threshold, or adjust the current-limit threshold with an external resistor-divider at ILIM_. Use a 2A to 20A divider current for accuracy and noise immunity. The current-limit threshold adjustment range is from 50mV to 200mV. In the adjustable mode, the current-limit threshold voltage equals precisely 1/10th the voltage seen at ILIM_. The logic threshold for switchover to the 75mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSH_ and CSL_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Power-Good Output (PGOOD)
CBYP
MAX1533A/MAX1537A
MAX1533A MAX1537A
LDO5 (RBST)* CBST DH NH L DBST
BST
INPUT (VIN)
LX LDO5 DL (CNL)* GND NL
PGOOD is the open-drain output of a comparator that continuously monitors both SMPS output voltages for undervoltage conditions. PGOOD is actively held low in shutdown (SHDN or ON3 or ON5 = GND), soft-start, and soft-shutdown. Once the digital soft-start terminates, PGOOD becomes high impedance as long as both outputs are above 90% of the nominal regulation voltage set by FB_. PGOOD goes low once either SMPS output drops 10% below its nominal regulation point, an output overvoltage fault occurs, or either SMPS controller is shut down. For a logic-level PGOOD output voltage, connect an external pullup resistor between PGOOD and VCC. A 100k pullup resistor works well in most applications. PGOOD is independent of the fault protection states OVP and UVP.
Fault Protection
Output Overvoltage Protection (OVP) If the output voltage of either SMPS rises above 111% of its nominal regulation voltage and the OVP protection is enabled (OVP = GND), the controller sets the fault latch, pulls PGOOD low, shuts down both SMPS controllers, and immediately pulls DH_ low and forces DL_
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING-NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry
FAULT PROTECTION 0.7 x INT REF_ 1.11 x INT REF_ INTERNAL FB
POWER-GOOD 0.9 x INT REF_
ENABLE OVP ENABLE UVP BLANK (POWER-UP) FAULT LATCH FAULT
TIMER
POR
POWERGOOD
Figure 7. Power-Good and Fault Protection ______________________________________________________________________________________ 25
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
high. This turns on the synchronous-rectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. However, immediately latching DL_ high typically causes slightly negative output voltages due to the energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the battery fuse blows. Cycle VCC below 1V or toggle either ON3, ON5, or SHDN to clear the fault latch and restart the SMPS controllers. Connect OVP to VCC to disable the output overvoltage protection. Output Undervoltage Protection (UVP) Each SMPS controller includes an output UVP protection circuit that begins to monitor the output 6144 clock cycles (1 / f OSC ) after that output is enabled (ON_ pulled high). If either SMPS output voltage drops below 70% of its nominal regulation voltage and the UVP protection is enabled (UVP = GND), the UVP circuit sets the fault latch, pulls PGOOD low, and shuts down both controllers using discharge mode (see the Output Discharge (Soft-Shutdown) section). When an SMPS output voltage drops to 0.3V, its synchronous rectifier turns on, clamping the discharged output to GND. Cycle V CC below 1V or toggle either ON3, ON5, or SHDN to clear the fault latch and restart the SMPS controllers. Connect UVP to VCC to disable the output undervoltage protection.
Table 5. Operating Modes Truth Table
MODE Power-Up Run Output Overvoltage Protection (OVP) Output Undervoltage Protection (UVP) CONDITION LDO5 < UVLO threshold. SHDN = high, ON3 or ON5 enabled. Either output > 111% of nominal level, OVP = low. Either output < 70% of nominal level, UVP is enabled 6144 clock cycles (1 / fOSC) after the output is enabled and UVP = low. COMMENTS Transitions to discharge mode after VIN POR and after REF becomes valid. LDO5, LDO3, REF remain active. DL_ is active if OVP is low. Normal operation. Exited by POR or cycling SHDN, ON3, or ON5. Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not high, DL3 and DL5 go high after discharge.
Discharge
OVP is low and either SMPS output is still high in either standby mode or shutdown mode.
Discharge switch (10) connects CSL_ to PGND. This is a temporary state entered when LDO5 is undervoltage or on the way to output UVLO, standby, shutdown, or thermal-shutdown states. One SMPS can be in discharge mode while the other is in run mode. If both outputs are discharged to 0.3V (on CSL_), discharge mode transitions to the appropriate state. DL_ stays high if OVP is low. LDO3, LDO5 active. All circuitry off. Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not high, DL3 and DL5 go high before LDO5 turns off. Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Standby Shutdown Thermal Shutdown Switchover Fault
ON5 and ON3 < startup threshold, SHDN = high. SHDN = low. TJ > +160C. Excessive current on LDO3 or LDO5 switchover transistors.
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Thermal Fault Protection The MAX1533A/MAX1537A feature a thermal fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down both SMPS controllers using discharge mode (see the Output Discharge (Soft-Shutdown) section). When an SMPS output voltage drops to 0.3V, its synchronous rectifier turns on, clamping the discharged output to GND. Cycle V CC below 1V or toggle either ON3, ON5, or SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15C.
MAX1533A/MAX1537A
SECONDARY FEEDBACK
INA
LDOA
FIXED 12V ONA 5R REF (2.0V)
Auxiliary LDO Detailed Description (MAX1537A Only)
The MAX1537A includes an auxiliary linear regulator that delivers up to 150mA of load current. The output (LDOA) can be preset to 12V, ideal for PCMCIA power requirements, and for biasing the gates of load switches in a portable device. In adjustable mode, LDOA can be set to anywhere from 5V to 23V. The auxiliary regulator has an independent ON/OFF control, allowing it to be shut down when not needed, reducing power consumption when the system is in a low-power state. A flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low input-output differential voltage. If VINA - VLDOA falls below 0.8V, the low-side switch is turned on for a time equal to 33% of the switching period. This reverses the inductor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to operate in forward mode. The low impedance presented by the transformer secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing VINA - VLDOA back into regulation. The secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. In this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage.
R
ADJA 0.15V
Figure 8. Linear-Regulator Functional Diagram
100k and solve for R1 (resistance from LDOA to ADJA) using the following equation: V R1 = R2 LDOA - 1 VADJA where VADJA = 2V nominal.
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery-selector switches. If there is a choice at all, lower input voltages result in better efficiency.
Adjustable LDOA Voltage (Dual-Mode Feedback)
Connect ADJA to GND to enable the fixed, preset 12V auxiliary output. Connect a resistive voltage-divider at ADJA between LDOA and GND to adjust the respective output voltage between 5V and 23V (Figure 8). Choose R2 (resistance from ADJA to GND) to be approximately
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
* Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output-capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. * Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. * Inductor Operating Point. This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: IINDUCTOR = VOUT ( VIN - VOUT ) VIN fOSC L
Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + IINDUCTOR 2
Transformer Design (For the MAX1537A Auxiliary Output)
A coupled inductor or transformer can be substituted for the inductor in the 5V SMPS to create an auxiliary output (Figure 1). The MAX1537A is particularly well suited for such applications because the secondary feedback threshold automatically triggers DL5 even if the 5V output is lightly loaded. The power requirements of the auxiliary supply must be considered in the design of the main output. The transformer must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. The power ratings of the synchronous-rectifier MOSFETs and the current limit in the MAX1537A must also be adjusted accordingly. Extremes of low input-output differentials, widely different output loading levels, and high turns ratios can further complicate the design due to parasitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. Power from the main and secondary outputs is combined to get an equivalent current referred to the main output. Use this total current to determine the current limit (see the Setting the Current Limit section): ILOAD(MAX) = PTOTAL / VOUT5 where PTOTAL is the sum of the main and secondary outputs and ILOAD(MAX) is the maximum output current used to determine the primary inductance (see the Inductor Selection section).
Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT ( VIN - VOUT ) VIN fOSC ILOAD(MAX) LIR
For example: ILOAD(MAX) = 5A, VIN = 12V, VOUT = 5V, fOSC = 300kHz, 30% ripple current or LIR = 0.3. L= 5V x (12V - 5V) = 6.50H
12V x 300kHz x 5A x 0.3
Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
The transformer turns ratio (N) is determined by: VSEC + VFWD VOUT5 + VRECT + VSENSE where D MAX is the maximum duty factor (see the Electrical Characteristics table), T is the switching period (1 / fOSC), and T equals VOUT / VIN x T when in PWM mode, or L x 0.2 x IMAX / (VIN - VOUT) when in skip mode. The amount of overshoot during a full-load to noload transient due to stored inductor energy can be calculated as: VSOAR =
MAX1533A/MAX1537A
N=
where V SEC is the minimum required rectified secondary voltage, VFWD is the forward drop across the secondary rectifier, VOUT5(MIN) is the minimum value of the main output voltage, and VRECT is the on-state voltage drop across the synchronous-rectifier MOSFET. The transformer secondary return is often connected to the main output voltage instead of ground to reduce the necessary turns ratio. In this case, subtract VOUT5 from the secondary voltage (V SEC - V OUT5 ) in the transformer turns-ratio equation above. The secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60V. Common silicon rectifiers, such as the 1N4001, are also prohibited because they are too slow. Fast silicon rectifiers such as the MURS120 are the only choice. The flyback voltage across the rectifier is related to the VIN - VOUT difference, according to the transformer turns ratio: VFLYBACK = VSEC + (VIN - VOUT5) x N where N is the transformer turns ratio (secondary windings/primary windings), and VSEC is the maximum secondary DC output voltage. If the secondary winding is returned to VOUT5 instead of ground, subtract VOUT5 from V FLYBACK in the equation above. The diode's reverse-breakdown voltage rating must also accommodate any ringing due to leakage inductance. The diode's current rating should be at least twice the DC load current on the secondary output.
(ILOAD(MAX) )
2
L
2COUT VOUT
Setting the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The peak inductor current occurs at ILOAD(MAX) plus half the ripple current; therefore: I ILIMIT > ILOAD(MAX) + INDUCTOR 2 where ILIMIT equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the default setting, the minimum currentlimit threshold is 70mV. Connect ILIM_ to V CC for the default current-limit threshold. In adjustable mode, the current-limit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 500mV to 2V adjustment range corresponds to a 50mV to 200mV current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10A to prevent significant inaccuracy in the currentlimit tolerance. The current-sense method (Figure 9) and magnitude determine the achievable current-limit accuracy and power loss. Typically, higher current-sense limits provide tighter accuracy, but also dissipate more power. Most applications employ a current-limit threshold (VLIMIT) of 50mV to 100mV, so the sense resistor can be determined by: RSENSE = VLIMIT / ILIM For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur. VSAG = L ILOAD(MAX)
2COUT ( VIN x DMAX - VOUT ) ILOAD(MAX) ( T - T ) COUT
(
)
2
+
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
9a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. Alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 9b) with an equivalent time constant: L = CEQ x REQ RL where RL is the inductor's series DC resistance. In this configuration, the current-sense resistance equals the inductor's DC resistance (RSENSE = RL). Use the worstcase inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor
INPUT (VIN) DH_ LX_ NH CIN L RSENSE COUT
MAX1533A DL_ MAX1537A
GND CSH_ CSL_
NL
DL
a) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN) DH_ LX_ NH CIN INDUCTOR
MAX1533A DL_ MAX1537A
GND CSH_ CSL_
COUT NL DL REQ CEQ
b) LOSSLESS INDUCTOR SENSING
Figure 9. Current-Sense Configurations
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see the Output-Capacitor Stability Considerations section), the filter capacitor's ESR dominates the output voltage ripple. So the output capacitor's size depends on the maximum ESR required to meet the output voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P - P) = RESR ILOAD(MAX) LIR In idle mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode currentsense threshold (VIDLE = 0.2VLIMIT). In idle mode, the no-load output ripple can be determined as follows: VRIPPLE(P - P) = VIDLE RESR RSENSE selection, the ESR needed to support 25mVP-P ripple is 25mV / 1.5A = 16.7m. One 220F/4V Sanyo polymer (TPE) capacitor provides 15m (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. For low-input-voltage applications where the duty cycle exceeds 50% (VOUT / VIN 50%), the output ripple voltage should not be greater than twice the internal slopecompensation voltage: VRIPPLE 0.02 x VOUT where VRIPPLE equals IINDUCTOR x RESR. The worstcase ESR limit occurs when VIN = 2 x VOUT, so the above equation can be simplified to provide the following boundary condition: RESR 0.04 x L x fOSC Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: short/long pulses or cycle skipping resulting in a lower switching frequency. Instability occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering too early or skipping a cycle. Cycle skipping is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC-current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX1533A/MAX1537A
The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations). Output-Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: fESR where fESR = fOSC
1 2 RESR COUT
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. For an out-of-phase regulator, the total RMS current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of overlap as defined in Figure 10.
31
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
The 40/60 optimal interleaved architecture of the MAX1533A/MAX1537A allows the input voltage to go as low as 8.3V before the duty cycles begin to overlap. This offers improved efficiency over a regular 180 outof-phase architecture where the duty cycles begin to overlap below 10V. Figure 10 shows the input-capacitor RMS current vs. input voltage for an application that requires 5V/5A and 3.3V/5A. This shows the improvement of the 40/60 optimal interleaving over 50/50 interleaving and in-phase operation. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. Choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime. VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., SO-8, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1533A/ MAX1537A DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, crossconduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zerovoltage switched device when used in the step-down topology.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both
INPUT CAPACITOR RMS CURRENT vs. INPUT VOLTAGE
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: V 2 PD (NH Re sistive) = OUT (ILOAD ) RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH
5.0 4.5 4.0 3.5 IRMS (A) 3.0 2.5 2.0 1.5 1.0 0.5 0 6
IN PHASE 50/50 INTERLEAVING
40/60 OPTIMAL INTERLEAVING 5V/5A AND 3.3V/5A 8 10 12 14 16 18 20
VIN (V) INPUT RMS CURRENT FOR INTERLEAVED OPERATION IRMS = (IOUT5 - IIN)2 (DLX5 - DOL) + (IOUT3 - IIN)2 (DLX3 - DOL) + (IOUT5 + IOUT3 - IIN)2 DOL + IIN2 (1 - DLX5 - DLX3 + DOL) V DLX5 = OUT5 VIN V DLX3 = OUT3 VIN DOL = DUTY-CYCLE OVERLAP FRACTION
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION IRMS = ILOAD VOUT (VIN - VOUT) VIN
(
)
Figure 10. Input RMS Current 32
(VIN(MAX) ) Switching) =
2
CRSS fSW ILOAD IGATE
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC-adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage:
V 2 PD (NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX)
MAX1533A/MAX1537A
CBST =
QGATE 200mV
where QGATE is the total gate charge specified in the high-side MOSFET's data sheet. For example, assume the FDS6612A n-channel MOSFET is used on the high side. According to the manufacturer's data sheet, a single FDS6612A has a maximum gate charge of 13nC (VGS = 5V). Using the above equation, the required boost capacitance is: CBST = 13nC = 0.065F 200mV
Selecting the closest standard value. This example requires a 0.1F ceramic capacitor.
Applications Information
The absolute worst case for MOSFET power dissipation occurs under heavy-overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate: I ILOAD = ILIMIT - INDUCTOR 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3rd the load current. This diode is optional and can be removed if efficiency is not critical.
Duty-Cycle Limits
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (IDOWN) as much as it ramps up during the on-time (IUP). This results in a minimum operating voltage defined by the following equation:
1 - 1 ( VOUT + VDIS ) VIN(MIN) = VOUT + VCHG + h DMAX
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates:
where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. Maximum Input Voltage The MAX1533A/MAX1537A controllers include a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP. At the beginning of each cycle, if the output voltage is still
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33
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
above the feedback-threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 VIN(SKIP) = VOUT fOSC t ON(MIN) where fOSC is the switching frequency selected by FSEL. * When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. * Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSH_, CSL_).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN, COUT_, and DL _ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 to 100 mils wide if the MOSFET is 1 inch from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST_ diode and capacitor, LDO5 bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 11. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output-filter-capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all of the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_).
34
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High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN
CONNECT THE EXPOSED PAD TO ANALOG GND
VIA TO POWER GROUND
VIA TO REF BYPASS CAPACITOR MAX1533A TOP LAYER
VIA TO VCC BYPASS CAPACITOR
VIA TO REF PIN MAX1533A BOTTOM LAYER VIA TO VCC PIN
KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (SEE THE EVALUATION KIT)
DUAL n-CHANNEL MOSFET INDUCTOR
SINGLE n-CHANNEL MOSFETS
INDUCTOR DH LX DL COUT
CIN
COUT
INPUT OUTPUT OUTPUT GROUND COUT GROUND
CIN
INPUT
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 11. PC Board Layout
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35
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Pin Configurations (continued)
LDOA SKIP DH5 BST5 LX5 IN CSH5 TOP VIEW INA SHDN
Chip Information
TRANSISTOR COUNT: 6890 PROCESS: BiCMOS
36
35
34
33
32
31
30
29
28
ADJA ON5 ON3 ONA FSEL ILIM3 ILIM5 REF GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
27 26 25 24 23 22 21 20 19
CSL5 FB5 LDO5 DL5 PGND DL3 LDO3 FB3 CSL3
MAX1537A
PGDLY PGOOD UVP DH3 BST3 LX3
OVP
THIN QFN 6mm x 6mm
36
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CSH3
VCC
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX1533A/MAX1537A
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37
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers MAX1533A/MAX1537A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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